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ICs for TV
AN5829S
Sound multiplex decoder IC for the U.S. televisions
s Overview
0.40.25 0.45
Unit: mm
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
The AN5829S is a multiplex sound demodulation IC dedicated to the U.S. television and incorporates a bidirectional I2C interface (adjustment, mode SW), an AGC circuit and external stereo input switches (2 systems).
* Stereo demodulation, SAP demodulation, dbx noise reduction, AGC, external stereo input SW and I2C bus interface are integrated in a single chip * Bi-directional I2C bus makes it possible to monitor MPX input level, separation adjustment (3 places), mode changeover and receiving status. * Eliminated external parts (multi-sound block: 21 pieces 14 pieces * Lower power dissipation (VCC = 5 V, ITOT = 18 mA)
0.10.1
1.27
s Features
0.3
7.20.3 9.40.3
SOP024-P-0375A
s Applications
* Televisions and VCRs for the North American market
0.15 0.925
2.00.2
15.30.3
1
2
R out L out 4 1
AN5829S
GND
s Block Diagram
VCC
7
17
16
15
Out SW I2C Decoder Offset cancel Matrix AGC DAC
21
22
ZAP 18 19
20
PE SCL SDA
L+R demod
L+R filter
Pilot det.
75 s De-emph.
24 23 2 3 L-R demod Wide band expand L-R filter Offset cancel 5 Wide band RMS det. Wide band filter 8 6 SAP det. Noise det. Spectral expand Spectral RMS det. Spectral filter 11 10 (L-R)/SAP switch dbx De-emph. fH, 2fH Trap filter
13 12
AUX2 L AUX2 R AUX1 L AUX1 R
St. PLL
Pilot cancel
Stereo filter
MPX in SAP demod SAP out filter
14
Input VCA
SAP filter
Noise filter
9
ICs for TV
ICs for TV
s Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 AGC timing External input 1 L-ch External input 1 R-ch 75 s filter offset cancel dbx offset cancel Wideband timing VCC Wideband level sensor input Spectral filter Spectral timing Spectral level sensor input SAP noise level detection Description Pin No. 13 14 15 16 17 18 19 20 21 22 23 24 Description SAP carrier detection Composite input Pilot signal detection Stereo PLL filter GND SCL SDA PE for ZAP L-ch output R-ch output External input 2 R-ch. External input 2 L-ch.
AN5829S
s Absolute Maximum Ratings
Parameter Supply voltage Supply current Power dissipation
*2 *1
Symbol VCC ICC PD Topr Tstg
Rating 6.0 25 150 -20 to +75 -55 to +125
Unit V mA mW C C
Operating ambient temperature Storage temperature
*1
Note) The use of this IC, which builds in dbx-TV noise reduction, requires a license agreement with THAT Corporation. *1: Except fot the operating ambient temperature and storage temperature, all ratings are for Ta = 25C. *2: Ta = 75C
s Recommended Operating Range
Parameter Supply voltage Symbol VCC Range 4.5 to 5.5 Unit V
3
AN5829S
s Electrical Characteristics at VCC = 5 V, NR: On,Ta = 25C
Input level (at 100% modulation) L+R: 75 mV[rms] (pre-emphasis off) L-R: 150 mV[rms] (dbx noise reduction off) Pilot: 15 mV[rms] SAP: 45 mV[rms] (dbx noise reduction off) Parameter Total circuit current Mono output level Symbol ICC V0(MON) No signal f = 1 kHz, (mono) 100%mod f = 300 Hz, (mono) 30%mod f = 8 kHz, (mono) 30%mod f = 1 kHz, (mono) 100%mod Input short-circuit, BPF (A curve) f = 1 kHz, (mono) 100%mod f = 1 kHz, (L(R)-only) 100%mod f = 300 Hz, (L(R)-only) 30%mod f = 3 kHz, (L(R)-only) 30%mod f = 8 kHz, (L(R)-only) 30%mod f = 1 kHz, (L(R)-only) 100%mod f = 15.73 kHz, (fH), 15 mV[rms] fH, 2 fH Trap+BPF f = 15.73 kHz (fH) f = 15.73 kHz (fH) f = 1 kHz, (SAP) 100%mod f = 300 Hz, (SAP) 30%mod f = 3 kHz, (SAP) 30%mod f = 1 kHz, (SAP) 100% f = 78.7 kHz, (5fH),V= 45 mV[rms], BPF f = 78.7 kHz, (5fH) f = 78.7 kHz, (5fH) (SAP)1 kHz, 100%mod (Stereo) pilot-signal (Stereo) 1 kHz, 100%mod (SAP) carrier-signal (SAP) 1 kHz, 100%mod (Mono) 1 kHz, 100%mod (SAP) carrier-signal f = 1 kHz, VIN = 500 mV[rms] INT: (mono) 1 kHz, 100%mod EXT: f = 1 kHz, 500 mV[rms] INT: (mono) 1 kHz, 100%mod EXT: f = 1 kHz, 500 mV[rms] Conditions Min 11 430 - 0.5 -1.2 - 0.5 380 - 0.7 -1 -2.5 4 0.5 370 -1 -2.5 11 0.5 Typ 18 480 0 - 0.1 0 480 0 0 - 0.5 8 500 0 - 0.5
ICs for TV
Max 25
Unit mA
530 mV[rms] 0.5 0.7 0.7 -60 0.5 dB dB % dBV dB
Mono frequency characteristics-1 V1(MON) Mono frequency characteristics-2 V2(MON) Mono distortion ratio Mono noise level THD(MON) VN(MON)
(L), (R) output voltage difference VLR(MON) Stereo output level V0(ST)
580 mV[rms] 0.7 1 1.5 1 -60 13 5 dB dB dB % dBV mV[rms] dB
Stereo frequency characteristics-1 V1(ST) Stereo frequency characteristics-2 V2(ST) Stereo frequency characteristics-3 V3(ST) Stereo distortion ratio Stereo noise level Stereo discrimination level THD(ST) VN(ST) VTH(ST)
Stereo discrimination hysteresis VHY(ST) SAP output level V0(SAP)
680 mV[rms] 1 1 1.5 -70 26 5 -50 -50 -50 -56 50 50 50 dB dB % dBV mV[rms] dB dB dB dB dB dB dB dB
SAP frequency characteristics-1 V1(SAP) SAP frequency characteristics-2 V2(SAP) SAP distortion ratio SAP noise level SAP discrimination level SAP discrimination hysteresis SAP Stereo crosstalk Stereo SAP crosstalk SAP Mono crosstalk Mono SAP crosstalk AUX 1, AUX 2 to INT crosstalk INT, AUX 2 to AUX 1 crosstalk INT, AUX 1 to AUX 2 crosstalk 4 THD(SAP) VN(SAP) VTH(SAP) VHY(SAP) CT1 CT2 CT3 CT4 CT5 CT6 CT7
ICs for TV
s Electrical Characteristics at VCC = 5 V, NR: On,Ta = 25C (continued)
Parameter AGC gain 1*1
*1
AN5829S
Symbol VAGC1 VAGC2
Conditions f = 1 kHz, VIN(EXT) = 50 mV[rms] f = 1 kHz, VIN(EXT) = 500 mV[rms]
Min 67 180
Typ 100 270
Max
Unit
140 mV[rms] 390 mV[rms]
AGC gain 2 I2
C interface IACK VIHI VILO fImax Maximum pin 2 sink current at ACK 1 3.5 0 2 20 5.0 0.9 100 mA V V kbit/s
Sink current at ACK SCL, SDA signal input high level SCL, SDA signal input low level Input available maximum frequency
Note) *1: 00H register: D7 = 0, D6 = 1
* Design reference data
Note) The characteristics listed below are theoretical values based on the IC design and are not guaranteed.
Parameter Stereo separation (100%)-1 Stereo separation (100%)-2 Stereo separation (100%)-3 Stereo separation (100%)-4 Stereo separation (30%)-1 Stereo separation (30%)-2 Stereo separation (30%)-3 Stereo separation (30%)-4 Stereo separation (10%)-1 Stereo separation (10%)-2 Stereo separation (10%)-3 Stereo separation (10%)-4 I2 C interface
Symbol Sep100-1 Sep100-2 Sep100-3 Sep100-4 Sep30-1 Sep30-2 Sep30-3 Sep30-4 Sep10-1 Sep10-2 Sep10-3 Sep10-4
Conditions f = 300 Hz, (L(R)-only) 100%mod f = 1 kHz, (L(R)-only) 100 %mod f = 3 kHz, (L(R)-only) 100%mod f = 8 kHz, (L(R)-only) 100%mod f = 300 Hz, (L(R)-only) 30%mod f = 1 kHz, (L(R)-only) 30%mod f = 3 kHz, (L(R)-only) 30%mod f = 8 kHz, (L(R)-only) 30%mod f = 300 Hz, (L(R)-only) 10%mod f = 1 kHz, (L(R)-only) 10%mod f = 3 kHz, (L(R)-only) 10%mod f = 8 kHz, (L(R)-only) 10%mod
Min 20 17 20 10 22 20 22 14 20 20 20 14
Typ 35 28 35 18 35 35 35 22 35 35 30 22
Max 1.0 0.35 3.5
Unit dB dB dB dB dB dB dB dB dB dB dB dB s s s s s s s s s s s s
Bus free before start Start condition set-up time Start condition hold time Low period SCL, SDA High period SCL Rise time SCL, SDA Fall time SCL, SDA Data set-up time (write) Data hold time (write) Acknowledge set-up time Acknowledge hold time Stop condition set-up time
tBUF tSU.STA tHD.STA tLO tHI tr tf tSU.DAT tHD.DAT tSU.ACK tHD.ACK tSU.STO
4.0 4.0 4.0 4.0 4.0 0.25 0.3 0 4.0
5
AN5829S
s Electrical Characteristics at VCC = 5 V, NR: On,Ta = 25C (continued)
Start condition Slave address ACK Sub address ACK Data byte
ICs for TV
Stop condition ACK
SDA tBUF SCL tSU.STA tHDSTA tr tf tHI tLO tSU.DAT tHD.DAT tLO tSU.STO
s Terminal Equivalent Circuits
Pin No. 1 Equivalent circuit
VCC
Description AGC: AGC level sensor pin
DC voltage (V) 0.5 to 2.0
425
51 k
1
500
GND
2
VCC
AUXIL: External input1 L-ch input pin
2.2
2
20.7 k 13.8 k 2.2 V
GND
3
VCC
AUXIR: External input 1 R-ch input pin
2.2
3
20.7 k 13.8 k 2.2 V
GND
6
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 4 Equivalent circuit
VCC
AN5829S
Description OFCAN1: 75 s filter output Offset cancel pin
DC voltage (V) 2.2
524
4
80 k 80 k 2.2 V GND
5
VCC
OFCAN2: dbx output Offset cancel pin
2.2
524
5
80 k 80 k 2.2 V GND
6
7.5
VCC
WBTIME: Wide expander effective value detection recovery time set-up pin
2.2
6
29 29 15 GND
7 8
VCC
VCC: VCC pin WBDET: RMS detection circuit input pin of wide band expander
VCC 2.2
8
14.4 k
2.2 V
GND
7
AN5829S
s Terminal Equivalent Circuits (continued)
Pin No. 9
230 18 k
ICs for TV
Equivalent circuit
VCC
Description SPEFIL: Variable de-emphasis level adjusting pin
DC voltage (V) 2.2
9
230 18 k
2.2 V
GND
10
7.5
VCC
SPETIME: RMS detection recovery time pin of variable de-emphasis
0.2
10
29 29 15 GND
11
VCC
SPEDET: RMS detection circuit input pin of variable de-emphasis
2.2
11
3.2 k
2.2 V
GND
12
VCC
NOISEDET: Noise detecting pin of SAP malfunction-prevention-circuit(Mute SAP demodulation at detecting noise.)
VCC - 2 VBE
141 k
12
GND
8
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 13 Equivalent circuit
VCC
AN5829S
Description SAPDET: SAP signal carrier level detection pin
DC voltage (V) VCC - 2 VBE
163 k
13
GND
14
VCC
MPXIN: Composite signal input pin
2.2
14
524 54.4 k 2.2 V
GND
15
VCC
PILOTDET: Stereo pilot signal detection pin
2.2VCC - 2 VBE
136 k
15
GND
16
VCC
PLL: Stereo PLL low pass filter connection pin
VCC - 2 VBE
58 k
16
GND
17
GND: GND pin
0 9
AN5829S
s Terminal Equivalent Circuits (continued)
Pin No. 18
51 k
ICs for TV
Equivalent circuit
VCC
Description SCL: I2C bus clock input pin
DC voltage (V)
18
1.7 k
GND
19
51 k
VCC
SDA: I2C bus data input pin
2.2
19
1.7 k
GND
20
20
PE: Current application input pin for ZAP at final test
GND
21
VCC
L-OUT: L-ch. line out output pin
2.2
520
21
430
850
2.2 V
GND
10
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No. 22
VCC
AN5829S
Equivalent circuit
Description R OUT: R-ch. line out output pin
DC voltage (V) 2.2
520
22
430
850
2.2 V
GND
23
VCC
AUX2R: External input 2 L-ch. input pin
2.2
23
20.7 k 13.8 k 2.2 V
GND
24
VCC
AUX2L: External input 2 R-ch. input pin
2.2
24
20.7 k 13.8 k 2.2 V
GND
11
AN5829S
s Usage Notes
ICs for TV
1. AGC set-up method By turning on AGC, the AGC performs 0 dB at a small signal input, Boost at a medium signal and gain reduction at a big signal. It can also control the I/O characteristics of AGC by I2C as shown below: AGC characteristics
1V "00" "11" AGC = Off AGC = On "10" "01"
Output level (rms)
100 mV
10 mV Data of sub address 00H D7 D6 10 mV 100 mV 1V 10 V
1 mV 1 mV
Input level (rms)
2. Guarantee of I2C operating temperature I2C bus control operation at an operating ambient temperature is theoretially guranteed based on IC design by means of the inspection using about 50% faster clock speed at the normal temperature (Ta = 25C). Namely it is a theoretical value based on IC design, therefore it is not guranteed at the shipping inspection because the inspection under a high and low temperature is not conducted. 3. Electrostatic breakdown Pay attention to the following levels: Pin 6: 200 pF, 130 V Pin 10: 200 pF, 150 V Pin 22: 200 pF, 190 V
12
ICs for TV
s Technical Information
[1] I2C bus 1. Receiving mode
AN5829S
SDA
SCL Start condition Slave address Acknowledge bit Sub address Acknowledge bit Data Acknowledge Stop bit condition
10110110 B 6
00000010 0 2
10000000 8 0
Transmission message As transfer messages, SCL and SDA are transfered synchronouslly and serially. SCL is a constant clock frequency and SDA is address data for controlling a receiving side and is sent in parallel by synchronizing with SCL. Data are in principle sent by 8-bit 3-octet (byte) and there exists an acknowledge bit per octet. The frame structure is mentioned below: 1) Start condition When SDA becomes from high to low at SCL = high, the receiver gets ready to receive. 2) Stop condition When SDA becomes from low to high at SCL = high, the receiver stops receiving. 3) Slave address Specified for each device. If any addresses of other devices are sent, receiving will be stopped. 4) Sub-address Specified for each function. 5) Data Data for controlling 6) Acknowledge bit This is the bit that informs the master of data reception every octet. The master sends the high signal and the receiver sends back the low signal as shown with the dotted line in the above figure, thus the master acknowledges reception on the receiver side. If the low signal is not sent back, the reception will be stopped. Except for the start and stop conditions, SDA does not change at SCL = high.
13
AN5829S
s Technical Information
[1] I2C bus (continued) 1. Receiving mode (continued) 1) Enhances adjustment-free mechanism of the TV set thanks to DAC control 3 and 9 switches
ICs for TV
2) Auto-increment function * Sub address 0 *: Auto-increment mode (Data sequential transfer leads to the sequential change of sub address, so that the data is inputted.) * Sub address 8 *: Data renewal mode (With sequential data transfer, data are inputted in the same sub address.) 2C bus protocol 3) I * Slave address * Format (normal) S Slave address W A Sub address A Data byte AP
Start condition
Acknowledge bit Write Mode: 0
Stop condition
* Auto-increment mode/data renewal mode
S
Slave address W A
Sub address
A
Data 1
A
Data 2
A
Data n
AP
4) As the initial state of DAC is not guaranteed, never fail to input the following data in a power on mode. "06" register: "04" "00" register: adjustment data "01" register: adjustment data "02" register: "00" "05" register: adjustment data
2. Transmission mode (read mode) I2C bus protocol * Slave address: 10110111 (B7H) * Format S Slave address RA Data byte AP
Read Mode: 1
14
ICs for TV
s Technical Information (continued)
[1] I2C bus (continued) * Sub address byte and data byte format Write mode (slave add.: 10110110) Sub address "00" "01" "02" "05" "06" Upper MSB D7 D6 D5 Data byte D4 D3 D2 D1
AN5829S
Lower LSB D0
AGC adj. AUXselect 0: AUX1 1: AUX2 Adj.: 1 On L:VGA out R:VCO fH AUX SW 0: Off 1: On Mute: 1 On AGC L: Mute R: Mute 1 On
Input level adjustment High frequency separation adjustment 0 FMONO: 1 On L: L+R R: L+R 0 St/SAP (L+R)/SAP 0 SAP 0 SAP
Low frequency separation adjustment 0 0 = Don't care
Read mode (slave add.: 10110111) Upper MSB D7 D6 D5 Data byte D4 D3 D2 D1 Lower LSB D0 = Don't care
Pilot det. SAP det. 1 DET 1 DET
15
AN5829S
s Technical Information (continued)
[2] Noise detecting operation in SAP receiving mode
ICs for TV
L-R filter Stereo filter MPX 14 in Input VCA 5fH BPF SAP filter 150 kHz BPF Noise filter Noise det.
12
SW1 a b
SAP out filter
dbx Decoder
SAP det.
SAP det.
13
I2C Decoder
DC voltage comparater
Noise det.
75 s De-emph. Matrix dbx Decoder
SW2 a b c
21 L out
a b c
22 R out
Pin 14 input "02" register Pin 12, pin 13 DC voltage Noise: Small Noise: Large "00" "00" V12 > V13 V12 < V13
SW1
SW2
I2C SAP det. Pin 21, pin 22
b a
c a
3.5 V to 5 V 0 V to 0.9 V
SAP L+R
16
ICs for TV
s Application Circuit Example
VCC 5V R out 180 k 4.7 F L out 0.1 F 2.2 F 4 1
Out SW I2C Decoder Offset cancel DAC Matrix St. PLL Pilot cancel Offset cancel AGC
0.047 F 16
4.7 F 21
4.7 F 22
7
ZAP
17
20 18 19 PE
L+R demod L+R filter Pilot det. 75 s De-emph.
15
SCL SDA
Stereo filter L-R demod Wide band expand L-R filter
24 4.7 F AUX2 L 23 4.7 F AUX2 R 2 4.7 F AUX1 L 3 4.7 F AUX1 R 4.7 F 5
Wide band RMS det. Wide band filter
4.7 F
SAP demod SAP det. Noise det. SAP out filter Spectral expand (L-R)/SAP switch dbx De-emph.
MPX in
14
Input VCA
SAP filter
8 6
Spectral RMS det. Spectral filter
0.33 F 10 F(Ta) 11 10 9
fH, 2fH Trap filter
Noise filter
0.1 F 3.3 F(Ta) 0.022 F
13 0.1 F 0.1 F
12
AN5829S
17

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